1. Field
Aspects of the described technology relate generally to an apparatus and method for manufacturing a polycrystalline silicon thin film, and more particularly, to a Joule-heating crystallization apparatus and method.
2. Description of the Related Art
In general, amorphous silicon (a-Si) is disadvantageous in that it has low mobility of electrons, i.e., electric charge carriers, and has a low aperture ratio and is not appropriate for a CMOS process. Meanwhile, a polycrystalline silicon (poly-Si) thin film element is available for configuring a driving circuit, which is required for writing an image signal in pixels, on a substrate such as a pixel thin film transistor (TFT)-array, which is not possible with an amorphous silicon TFT. Thus, the polycrystalline silicon thin film element, in which connections between a plurality of terminals and a driver IC are not required, has high productivity and reliability and results in a smaller panel thickness.
Methods for manufacturing a polycrystalline silicon TFT include a method for manufacturing a polycrystalline silicon TFT in high temperature conditions and a method for manufacturing a polycrystalline silicon TFT in low temperature conditions. In order to form the polycrystalline silicon TFT in high temperature conditions, a high-priced material such as quartz or the like must be used as the material for a substrate, so the method for manufacturing a polycrystalline silicon TFT in high temperature conditions is not suitable for a large size. Thus, research for a method for manufacturing an amorphous silicon thin film with polycrystalline silicon in low temperature conditions is actively ongoing. Methods for forming polycrystalline silicon at a low temperature include solid phase crystallization (SPC), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), excimer laser crystallization (ELC), Joule-heating induced crystallization (JIC), and the like.
In particular, JIC is a crystallization method in which a conductive thin film is disposed on or under an amorphous silicon thin film, to which an electric field is applied to perform Joule heating to thereby perform crystallization. In JIC, an insulating layer is deposited on the amorphous silicon thin film and then patterned, and a conductive thin film is deposited on the patterned insulating layer and amorphous silicon thin film to allow a portion of the conductive thin film to be in contact with the amorphous silicon thin film through the patterned portion of the insulating layer. This is to prevent arc generation when a voltage is applied thereto. An electric field is applied to the amorphous silicon thin film through electrode terminals installed at both ends of an upper surface of the conductive thin film, on which Joule heating is then performed to crystallize the amorphous silicon thin film.
That is, as mentioned above, JIC requires the process of patterning the insulating layer to allow the portion of the conductive thin film to be in contact with the amorphous silicon thin film in order to prevent arc generation in the case of a voltage application and the process of forming the conductive thin film in order to apply an electric field to the amorphous silicon thin film.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the described technology, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.